In the manufacture of semiconductor devices it is important to have methods for testing a device and determining if it is a good device or if it contains defects before selling such a product to a customer. If the results of the test are within a manufacturer's tolerance levels then the device is presumably a good or non-defective device and may be sold to a customer. If the results are not the same and are not within the manufacturer's tolerance levels then the device is a defective device and cannot be sold to a customer.
One particular method for testing a device for defects is called IDDQ Testing. In a CMOS device when the clock is stopped, the device is said to be in a quiescent state, thus the current in the device is called drain to drain quiescent current (IDDQ). IDDQ derives from quiescent IDD which is the current drawn by the Vdd power supply. The Vdd supply is typically held at a voltage above ground and fixed within narrow bounds. The other supply is typically called Vss and is taken to be ground (i.e. arbitrarily assigned a value of zero electrical potential. In IDDQ testing, a device is tested by measuring the current while the device is in the quiescent state. Since defects often result in significant leakage currents, measuring the quiescent current allows defects such as open and short circuits to be detected. If the IDDQ is above a preset threshold, then the device is termed "defective" and is not sold to the customer.
Prior methods for IDDQ testing require a low background leakage current while in the quiescent state. In such prior methods, the background leakage current is typically required to be less than a few hundred microamps (.mu.A). As is illustrated in FIG. 1, a statistical sample of devices under test (DUTs) is taken in order to determine a median background leakage current 110. Once a median background leakage current is established then an IDDQ pass/fail limit 120 is set. The pass/fail limit must be set such that it is greater than the median background leakage current but such that it is less than the average current caused by a device defect. Typically in prior methods the pass/fail limit is set at a current much higher than the median, usually from three (3) to six (6) standard deviations greater than the median background leakage current. For example, the pass/fail limit may be in the range of approximately 500 microamps (.mu.A) to 1.5 milliamps (mA). Any device exhibiting an IDDQ current greater than the pass/fail limit is assumed to be a defective device 130 and is not sold to a customer.
One of the problems with prior art methods for IDDQ testing is that they can only detect defects where the defect causes an IDDQ current larger than the background leakage current. As device dimensions of semiconductor devices become smaller and more dense, the background leakage current increases in relation to the defect currents which must be resolved.
This increase in background leakage current can be traced to several factors. The most prominent of these are the increase in the number of devices on a single substrate and an increase in the subthreshold leakage across a given device as the length of its polysilicon gate decreases. The latter, in turn, can be divided into several components, each of which contributes a share to the total current. For example in submicron CMOS devices, background leakage currents in the range of approximately several tens of milliamps (mA) are likely due to the short channel lengths.
As is illustrated in FIG. 2, a wider distribution in background leakage current makes resolution of the same level of defect current problematic. Since the background leakage is higher, the pass/fail limit 220 must be increased proportionately to avoid the improper rejection of functional devices. Meanwhile, the standard deviation of the background leakage 230 has increased sufficiently to make resolution of smaller defect currents impossible.
An additional problem with current IDDQ testing is the variability of the background leakage current from wafer to wafer and from device to device within a wafer. In an ideal case, for example, the background leakage in a wafer should be I.sub.1 if there are no defects. When measuring the current of that wafer a different current I.sub.2 which is in excess of I.sub.1 is due to the existence of one or more defects. This difference in currents is attributable to the defect equal to I.sub.2 -I.sub.1. This is a magnitude which can be differentiated on a tester. The problem, however, is not solving this differential between the magnitude of the defects, but rather is determining the actual background leakage current when shifting from wafer to wafer. For example, wafer1 may have a background current of I.sub.1, wafer2 may have a current of 12, and wafer3 may have a background current of I.sub.3.
Currently, an average or median is calculated for the background leakage current for a number of wafers. As illustrated in FIGS. 3a and 3b, the number of wafers measured may vary. The fewer number of wafers measured in FIG. 3a exhibits a magnitude 310a and a variability 320a. The variability 320a is illustrated by the difference between the sides of the bell curve. In FIG. 3b, a larger number of wafers are measured and although the magnitude 310b is lower than the magnitude 310a of FIG. 3a, the variability 320b is twice as large as the variability 320a, in FIG. 3a. In other words, from FIGS. 3a and 3b, it can be observed that a given defect can be resolved only if the additional current due to the defect (I.sub.2 -I.sub.1) is significantly greater than the standard deviation of the background leakage current over the sample size. As illustrated in FIGS. 3a and 3b, while the distribution in FIG. 3b has an identical mean value (I.sub.average) as the distribution in FIG. 3a, its higher standard deviation makes the resolution of some of the defects nearly impossible. Thus, the larger number of wafers tested the larger the variability of the background leakage current from wafer to wafer.
When testing devices for defects, if the background leakage current was the same from wafer to wafer, it would be relatively simple to set the pass/fail criteria for determining if a device defect exists. For example, if it is known that every device on every wafer being tested has a background leakage current of 5.0 mA, whatever is in excess of 5.0 mA would necessarily correspond to a defect. For instance, an IDDQ measurement of a device is determined to be 5.2 mA. The portion of that IDDQ measurement attributable to the background leakage current is 5.0 mA, and the remaining 0.2 mA (200 .mu.A) is attributable to a defect. However, as is illustrated in FIGS. 3a and 3b, the background leakage current varies from wafer to wafer. This variability of the background leakage current from wafer to wafer may cause considerable problems in determining if a defect exists from one wafer to the next.
In the prior art a mean (or average) background leakage current is used to set the pass/fail limit for determining device defects (i.e. in the prior art the pass/fail limit is set several standard deviations larger than the mean background leakage current). Since an average background leakage current is used, those devices with a background leakage current much less than the mean that still contain a defect may not be screened out because the background defect current and the defect current combined may not exceed the mean background leakage current or the pass/fail limit set by using such a mean. Also, those devices with a background leakage current much larger than the mean that do not contain a defect, but still exceed the mean background leakage current or the pass/fail limit set by using such a mean, are screened out as being defective, when they are actually good devices.
As the variability of the devices will change with the number of wafers being tested, so to will the average of that variability. The more devices you test the more the average will change either higher or lower depending upon the background leakage current measured in each device. Some prior art methods have tried to combat this problem by trying to lower the average background leakage using low temperature testing or by using multiple power grids. Each of these methods have significant disadvantages.
For example, in order for low temperature testing to be effective, the temperature would have to be brought very low. Significantly lowering the temperature of a wafer in a device may cause problems in future processing and could cause condensation in some of the devices so that they would not work later. Using multiple power grids imposes difficulty for device design because of the need to expand pin count to match background leakage. Multiple power grids also pose noise problems due to use of multiple V.sub.cc busses.
Thus, what is needed is a method for IDDQ testing which takes into account not only the magnitude of the background leakage currents, but also the variability from device to device of the background leakage current.